Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution.

Jack L Mason; Gregory Simco

doi:10.1109/mtv.2013.27

Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution.

Jack L Mason
, Gregory Simco

Research output: Contribution to conference › Presentation

1 Scopus citations

Abstract

Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.

Original language	American English
Pages	74-76
Number of pages	3
DOIs	https://doi.org/10.1109/mtv.2013.27
State	Published - Oct 15 2014
Event	MTV ’13 Proceedings of the 2013 14th International Workshop on Microprocessor Test and Verification - Duration: Dec 13 2014 → …

Conference

Conference	MTV ’13 Proceedings of the 2013 14th International Workshop on Microprocessor Test and Verification
Period	12/13/14 → …

Bibliographical note

Publisher Copyright:
© 2013 IEEE.

ASJC Scopus Subject Areas

General Engineering

Keywords

computer architecture
digital stimulation
multi-threading
parallel processing
program testing
software architecture
speculative execution
target environment
validation testing
system simulation

Disciplines

Computer Sciences

Access to Document

10.1109/mtv.2013.27

Cite this

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title = "Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution.",

abstract = " Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.",

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AU - Simco, Gregory

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N2 - Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.

AB - Due to simulation overhead, validation of proposed microarchitecture enhancements may be limited to simple test scenarios, which focus on the known architectural deficiencies. These test scenarios often avoid a complete simulation of the eventual target environment in which the enhancements will be employed. A case study is presented, comparing and contrasting the performance of previous Thread-Level Speculation (TLS) proposals with that of a new, context-preserving proposal. Validation is performed within the constraints of a simulated target environment.

KW - computer architecture

KW - digital stimulation

KW - multi-threading

KW - parallel processing

KW - program testing

KW - software architecture

KW - speculative execution

KW - target environment

KW - validation testing

KW - system simulation

UR - https://nsuworks.nova.edu/gscis_facpres/40

UR - http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6926105

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DO - 10.1109/mtv.2013.27

M3 - Presentation

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EP - 76

T2 - MTV ’13 Proceedings of the 2013 14th International Workshop on Microprocessor Test and Verification

Y2 - 13 December 2014

ER -

Target Environment Simulation and its Impact on Architecture Validation: A Case Study of Thread-Level Speculative Execution.

Abstract

Conference

Bibliographical note

ASJC Scopus Subject Areas

Keywords

Disciplines

Access to Document

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Cite this